//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================

#ifndef __ELASTOS_UART_H__
#define __ELASTOS_UART_H__

#define COMPORT_AVAILABLE(comPort) \
        (ComPort1 == (comPort) || ComPort2 == (comPort) ||ComPort3 == (comPort) )

#define COMPORT_IOBASE(comPort) \
        ((ComPort1 == (comPort))? _UART1_IOBASE :\
        ((ComPort2 == (comPort))?  _UART2_IOBASE : _UART3_IOBASE))

// UART IO base address
#define FFUART_IOBASE       ((ioport_t)0x80100000)
#define BTUART_IOBASE       ((ioport_t)0x80200000)
#define STUART_IOBASE       ((ioport_t)0x80700000)

#define _UART1_IOBASE       FFUART_IOBASE
#define _UART2_IOBASE       BTUART_IOBASE
#define _UART3_IOBASE       STUART_IOBASE

// UART registers' address
#define _UART_RBR(base)     ((ioport_t)((base) + 0x00))
#define _UART_THR(base)     ((ioport_t)((base) + 0x00))
#define _UART_IER(base)     ((ioport_t)((base) + 0x04))
#define _UART_IIR(base)     ((ioport_t)((base) + 0x08))
#define _UART_FCR(base)     ((ioport_t)((base) + 0x08))
#define _UART_LCR(base)     ((ioport_t)((base) + 0x0C))
#define _UART_MCR(base)     ((ioport_t)((base) + 0x10))
#define _UART_LSR(base)     ((ioport_t)((base) + 0x14))
#define _UART_MSR(base)     ((ioport_t)((base) + 0x18))
#define _UART_SPR(base)     ((ioport_t)((base) + 0x1C))
#define _UART_ISR(base)     ((ioport_t)((base) + 0x20))
#define _UART_DLL(base)     ((ioport_t)((base) + 0x00))
#define _UART_DLH(base)     ((ioport_t)((base) + 0x04))

// Interrupt Enable Register (IER)
#define IER_RAVIE           0x01
#define IER_TIE             0x02
#define IER_RLSE            0x04
#define IER_MIE             0x08
#define IER_RTOIE           0x10
#define IER_NRZE            0x20
#define IER_UUE             0x40
#define IER_DMAE            0x80

// Line Control Register (LCR)
#define LCR_WL_5            0x00    // Word Length 5 Bits
#define LCR_WL_6            0x01    // Word Length 6 Bits
#define LCR_WL_7            0x02    // Word Length 7 Bits
#define LCR_WL_8            0x03    // Word Length 8 Bits
#define LCR_SB_1            0x00    // 1 Stop Bit
#define LCR_SB_1_5          0x04    // 1.5 Stop Bit
#define LCR_SB_2            LCR_SB_1_5  // 2 Stop Bit
#define LCR_NP              0x00    // No Parity
#define LCR_OP              0x08    // Odd Parity
#define LCR_EP              0x18    // Even Parity
#define LCR_HP              0x28    // High Parity (Sticky)
#define LCR_LP              0x38    // Low Parity (Sticky)
#define LCR_SB              0x40    // Set Break Enable
#define LCR_DLAB            0x80    // Divisor Latch Access Bit

// Baud-Rate Divisor
#define BAUDDIV_300         3072
#define BAUDDIV_1200        768
#define BAUDDIV_2400        384
#define BAUDDIV_4800        192
#define BAUDDIV_9600        96
#define BAUDDIV_19200       48
#define BAUDDIV_38400       24
#define BAUDDIV_57600       16
#define BAUDDIV_115200      8

// Line Status Register (LSR)
#define LSR_DR              0x01    // Data Ready
#define LSR_OE              0x02    // Overrun Error
#define LSR_PE              0x04    // Parity Error
#define LSR_FE              0x08    // Framing Error
#define LSR_BI              0x10    // Break Interrupt
#define LSR_TDRQ            0x20    // Transmit Data Request
#define LSR_TEMT            0x40    // Transmitter Empty
#define LSR_FIFOE           0x80    // FIFO Error Status
#define LSR_ERRS            (LSR_OE | LSR_PE | LSR_FE) // Error mask

// FIFO Control Register (FCR)
#define FCR_TRFIFOE         0x01    // Transmit and Receive FIFO Enable
#define FCR_RESETRF         0x02    // Reset Receive FIFO
#define FCR_RESETTF         0x04    // Reset Transmit FIFO

#endif // __ELASTOS_UART_H__
